1. Field of the Invention
The present invention relates to an image pickup apparatus that acquires image information.
2. Description of the Related Art
A configuration in which drive signals are supplied to an image sensor and an A/D converter using a timing generator is known as a configuration for peripheral circuitry of an image sensor provided in an image pickup apparatus. For example, Japanese Patent Laid-Open No. 2003-319133 discloses a configuration in which drive signals are supplied by a control and drive clock generator to a CCD line sensor and an A/D converter.
FIG. 4 is a diagram illustrating a configuration for the peripheral circuitry of an image sensor provided in an image pickup apparatus according to the related art. A CPU 101 controls a timing generator 102, a CMOS sensor 103, and an A/D converter 104. The timing generator 102 generates and outputs an image sensor reference signal for driving the CMOS sensor 103 and an A/D converter drive signal for driving the A/D converter 104. The CMOS sensor 103 includes a photoelectric converter 105, a drive signal generation unit 106, and a serial interface 107. The photoelectric converter 105 converts light resulting from an original image into an analog image signal. The drive signal generation unit 106 generates an image sensor drive signal necessary for the photoelectric conversion. The serial interface 107 sends/receives control signals to/from the CPU 101. The A/D converter 104 converts the analog image signal into a digital image signal in accordance with the A/D converter drive signal received from the timing generator 102, and outputs that digital image signal.
Meanwhile, the drive signal generation unit 106 of the CMOS sensor 103 receives the image sensor reference signal outputted by the timing generator 102. The drive signal generation unit 106 then generates an image sensor drive signal required for the photoelectric conversion based on a synchronization signal and a reference clock included in the image sensor reference signal. The photoelectric converter 105 outputs the analog image signal in accordance with the image sensor drive signal.
FIG. 5 is a diagram illustrating the drive signal generation unit 106. A register 502 holds setting values included in control signals received from the CPU 101 via the serial interface 107 (FIG. 4). A counter 503 counts in synchronization with the reference clock included in the image sensor reference signal. A comparator 504 generates the image sensor drive signal and a mask signal by comparing the setting values held in the register 502 with the counter value of the counter 503. A mask unit 505 partially masks the image sensor reference signal in accordance with the mask signal from the comparator 504.
Incidentally, the analog image signal outputted by the CMOS sensor 103 is output so as to be delayed relative to the image sensor reference signal. This is due to the fact that signal delay occurs within the photoelectric converter 105 and the drive signal generation unit 106.
Meanwhile, the A/D converter 104 converts the analog image signal output by the CMOS sensor 103 to a digital image signal based on the A/D converter drive signal output by the timing generator 102, and outputs the digital image signal to a circuit in a later stage (for example, a shading circuit or the like).
It is necessary for the synchronization and phase relationships to be continuously maintained between the image signals and the drive signals of the various elements in order for a system that transmits such image signals to correctly transmit and process images. If the synchronization and phase relationships break down, the main scanning position becomes shifted, the A/D converter cannot correctly perform the A/D conversion, and so on.
The amount of delay of the analog image signal described above depends on changes in environmental conditions, such as the ambient temperature and operation state of the image sensor, the voltage of the power source, and so on, and thus is not constant. For this reason, with an image pickup apparatus configured as above, as the driving frequency of the image sensor increases, the variation in the amount of delay of the analog image signal output from the image sensor also increases relative to one pixel period of the digital image signal output from the A/D converter. This results in a breakdown of the synchronization relationship or phase relationship between the analog image signal and the drive signals of the elements in the elements of later stages (for example, the A/D converter), ultimately making correct image processing impossible.
FIG. 6 is a diagram illustrating an example of input/output signals in the image sensor. A CLK_IN signal and a SYNC_IN signal are signals included in the image sensor reference signal, and are input to the CMOS sensor 103. The CLK_IN signal is a reference clock for image transmission. The SYNC_IN signal is an image synchronization signal synchronized with the reference clock, and is a signal that, for example, indicates the main scanning start position for the image. The various elements hold the image in synchronization based on these signals. The CLK_IN signal and the SYNC_IN signal are also included in the image sensor drive signal and the A/D converter drive signal, and are input to the CMOS sensor 103 and the A/D converter 104. The CMOS sensor 103 outputs the analog image signal using the CLK_IN signal and the SYNC_IN signal as references.
At that time, the timing at which the analog image signal is output by the image sensor is delayed relative to the timing at which the reference clock is input to the image sensor. This delay varies depending on the environmental conditions mentioned above. To put it differently, the timing at which the analog image signal (DATA) is output fluctuates between a minimum signal delay (DATA_minDELAY) and a maximum signal delay (DATA_maxDELAY).
If this variation becomes greater than a single cycle of the reference clock, the synchronization relationship between the SYNC_IN signal and the analog image signal breaks down, making it impossible to correctly transmit image signals. It becomes less and less possible to ignore the variation in the signal delay the higher the frequency of the reference clock becomes.
However, even if the variation remains less than a single cycle of the reference clock, an increase in the proportion of the variation relative to the reference clock will lead to a change in the phase relationship between the analog image signal and the A/D converter drive signal in the A/D converter in a later stage. Accordingly, the timing at which the analog image signal is sampled cannot be uniquely determined, and thus the analog image signal cannot be correctly converted into a digital image signal.